In high-speed input/output (I/O or IO) links, an accurate measurement of the eye width of the received signal is critically important. The output of a signal from an I/O circuit transmitter is known commonly as an eye diagram. Eye diagrams help determine system level voltages and timing margins associated with high speed I/O operations; hence, the better the quality of the digital signal transmission, the wider the eye width and eye height.
In some current data eye training techniques, a Phase Interpolator (PI) is used to move the sampling clock to two sides/edges (right and left) of the data eye until a failure is detected. PI control codes for the failing positions may be captured. The average of the right and left edge control codes may determine the eye center. PI may be finally programmed with the average value of the right and left eye edge PI codes to put the sampling clock at the center of data valid window. If PI steps are not uniform, this method of PI training will have an offset to real data center.
However, as process technology improves in dimensions, it becomes very hard to design PI with uniform steps over the operating range of the PI. This causes the trained PI clock to have an offset from the real data eye center. This offset adversely affects the system timing margin and limits the bandwidth of the I/O interconnect.